The AXI L2 port of each R5F core
integrates a remote L2 cache controller with integrated tag RAM. AXI is a bus
protocol defined by ARM and stands for Advanced eXtensible Interface. The L2 cache
is remote which means the cache data memory is allocated from the available L2 SRAM
in the device. Once allocated, this SRAM space is unavailable for application code /
data.
RL2 supports the following features:
- Integrated tag RAM with 4096 cache lines support
- Eight-way set associative with LRU policy
- RL2 cache line size is aligned with R5F cache line size (32 bytes)
- ECC protection on tag RAM
- Software programmable cache lines to enable application configurable remote
cache size of 8KB, 16KB, 32KB, 64KB or 128KB
- The cache-able target space varies proportionately based on the cache
size.
- Dual mode support to enable
sharing two cache lines the same way which increases the remote cache size to
256kB while reducing the cache-able region of tag RAM
- Pass-through for addresses not within the cache-able region
- Pass-through for accesses originating from FLC DMA
- Supports signaling of XIP read pending signal that allows automatic hardware
priority of XIP during read-while-write operations for flash
firmaware-over-the-air update (FOTA)