SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Event Trigger Pre-Scale Register
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| Instance Name | Physical Address |
|---|---|
| EPWM0 | 2300 0034h |
| EPWM1 | 2301 0034h |
| EPWM2 | 2302 0034h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED1 | INTCNT | INTPRD | |||||
| R | R | R/W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:4 | RESERVED1 | R | 0h | Reserved |
| 3:2 | INTCNT | R | 0h | ePWM Interrupt Event [EPWMx_INT] Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred These bits are automatically cleared when an interrupt pulse is generated If interrupts are disabled, ETSEL[INT] = 0 or the interrupt flag is set, ETFLG[INT] = 1, the counter will stop counting events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD] 0h No events have occurred 1h 1 event has occurred 2h 2 events have occurred 3h 3 events have occurred |
| 1:0 | INTPRD | R/W | 0h | ePWM Interrupt [EPWMx_INT] Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated To be generated, the interrupt must be enabled [ETSEL[INT] = 1] If the interrupt status flag is set from a previous interrupt [ETFLG[INT] = 1] then no interrupt will be generated until the flag is cleared via the ETCLR[INT] bit This allows for one interrupt to be pending while another is still being serviced Once the interrupt is generated, the ETPS[INTCNT] bits will automatically be cleared Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear Writing a INTPRD value that is less than the current counter value will result in an undefined state If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written, the counter is incremented 0h Disable the interrupt event counter. No
interrupt will be generated and the
EPWM_ETFRC[0] INT bit is ignored.
1h Generate an interrupt on the first event
INTCNT = 0b01 (first event)
2h Generate interrupt on the EPWM_ETPS[3-2]
INTCNT = 0b10 (second event)
3h Generate interrupt on the EPWM_ETPS[3-2]
INTCNT = 0b11 (third event) |