SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | Dependencies |
|---|---|---|---|---|---|---|---|
| ADC0 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_ADC | 41 | OFF | YES | LPSC_MAIN_IP0 |
| Module Instance | Source | Description |
|---|---|---|
| ADC0 | MAIN_PSC0 | ADC0 reset |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| ADC0 | ADC0_ecc_corrected_err_level_0 | ESM0_esm_lvl_event_IN_33 | ESM0 | ADC0 interrupt request | level |
| ADC0 | ADC0_ecc_uncorrected_err_level_0 | ESM0_esm_lvl_event_IN_34 | ESM0 | ADC0 interrupt request | level |
| ADC0 | ADC0_fifo0_pulse_0 | PDMA5_adc12_0_rx_IN_0 | PDMA5 | ADC0 interrupt request | pulse |
| ADC0 | ADC0_fifo1_pulse_0 | PDMA5_adc12_0_rx_IN_1 | PDMA5 | ADC0 interrupt request | pulse |
| ADC0 | ADC0_gen_level_0 | C7X256V0_CLEC_gic_spi_IN_151 | C7X256V0_CLEC | ADC0 interrupt request | level |
| ADC0 | ADC0_gen_level_0 | C7X256V1_CLEC_gic_spi_IN_151 | C7X256V1_CLEC | ADC0 interrupt request | level |
| ADC0 | ADC0_gen_level_0 | R5FSS0_CORE0_intr_IN_151 | R5FSS0_CORE0 | ADC0 interrupt request | level |
| ADC0 | ADC0_gen_level_0 | R5FSS0_CORE1_intr_IN_151 | R5FSS0_CORE1 | ADC0 interrupt request | level |
| ADC0 | ADC0_gen_level_0 | R5FSS1_CORE0_intr_IN_151 | R5FSS1_CORE0 | ADC0 interrupt request | level |
| ADC0 | ADC0_gen_level_0 | R5FSS1_CORE1_intr_IN_151 | R5FSS1_CORE1 | ADC0 interrupt request | level |
| ADC0 | ADC0_gen_level_0 | WKUP_R5FSS0_CORE0_intr_IN_151 | WKUP_R5FSS0_CORE0 | ADC0 interrupt request | level |
| Module Instance | Module Clock Input | Source Clock Signal | Source Control Register | Description |
|---|---|---|---|---|
| ADC | ADC_CLK | HFOSC0_CLKOUT | ADC0_CLKSEL[1:0] | |
| HFOSC1_CLKOUT | ADC0_CLKSEL[1:0] | |||
| MAIN_PLL1_HSDIV4_CLKOUT | ADC0_CLKSEL[1:0] | |||
| EXT_REFCLK1 | ADC0_CLKSEL[1:0] | |||
| SYS_CLK | MAIN_SYSCLK0 | |||
| VBUS_CLK | MAIN_SYSCLK0/2 |