SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Interrupt Enable Set Register 0
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| Instance Name | Physical Address |
|---|---|
| FSS1_HYPERBUS1P0_0 | 0072 2080h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | MEM_ARID_FIFO_ENABLE_SET | MEM_AR_FIFO_ENABLE_SET | MEM_AWID1_FIFO_ENABLE_SET | MEM_WID1_FIFO_ENABLE_SET | MEM_AW1_FIFO_ENABLE_SET | MEM_AWID0_FIFO_ENABLE_SET | MEM_WID0_FIFO_ENABLE_SET |
| NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MEM_AW0_FIFO_ENABLE_SET | MEM_RX_FIFO_ENABLE_SET | MEM_RDAT_FIFO_ENABLE_SET | MEM_BDAT1_FIFO_ENABLE_SET | MEM_BDAT0_FIFO_ENABLE_SET | MEM_WDAT1_FIFO_ENABLE_SET | MEM_WDAT0_FIFO_ENABLE_SET | MEM_ADR_FIFO_ENABLE_SET |
| R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:15 | RESERVED | NONE | 0h | Reserved |
| 14 | MEM_ARID_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_arid_fifo_pend |
| 13 | MEM_AR_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_ar_fifo_pend |
| 12 | MEM_AWID1_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_awid1_fifo_pend |
| 11 | MEM_WID1_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_wid1_fifo_pend |
| 10 | MEM_AW1_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_aw1_fifo_pend |
| 9 | MEM_AWID0_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_awid0_fifo_pend |
| 8 | MEM_WID0_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_wid0_fifo_pend |
| 7 | MEM_AW0_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_aw0_fifo_pend |
| 6 | MEM_RX_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_rx_fifo_pend |
| 5 | MEM_RDAT_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_rdat_fifo_pend |
| 4 | MEM_BDAT1_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_bdat1_fifo_pend |
| 3 | MEM_BDAT0_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_bdat0_fifo_pend |
| 2 | MEM_WDAT1_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_wdat1_fifo_pend |
| 1 | MEM_WDAT0_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_wdat0_fifo_pend |
| 0 | MEM_ADR_FIFO_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for mem_adr_fifo_pend |