SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Enhanced Feature Register
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0008h |
| UART1 | 0281 0008h |
| UART2 | 0282 0008h |
| UART3 | 0283 0008h |
| UART4 | 0284 0008h |
| UART5 | 0285 0008h |
| UART6 | 0286 0008h |
| WKUP_UART0 | 2B30 0008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AUTO_CTS_EN | AUTO_RTS_EN | SPECIAL_CHAR_DETECT | ENHANCED_EN | SW_FLOW_CONTROL | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | NONE | 0h | Reserved |
| 7 | AUTO_CTS_EN | R/W | 0h | Auto-CTS enable bit. 0: Normal operation. 1: Auto-CTS flow control is enabled i.e. transmission is halted when the CTS* pin is high (inactive). Reset Source: mod_g_arstn |
| 6 | AUTO_RTS_EN | R/W | 0h | Auto-RTS enable bit. 0: Normal operation. 1: Auto- RTS flow control is enabled i.e. RTS* pin goes high (inactive) when the receiver FIFO HALT trigger level, TCR[3:0], is reached, and goes low (active) when the receiver FIFO RESTORE transmission trigger level is reached. Reset Source: mod_g_arstn |
| 5 | SPECIAL_CHAR_DETECT | R/W | 0h | 0: Normal operation. 1: Special character detect enable. Received data is compared with XOFF2 data. If a match occurs the received data is transferred to RX FIFO and IIR bit 4 is set to 1 to indicate a special character has been detected. Reset Source: mod_g_arstn |
| 4 | ENHANCED_EN | R/W | 0h | Enhanced functions write enable bit. 0: Disables Writing to IER bits 4-7, FCR bits 4-5, and MCR bits 5-7. 1: Enables Writing to IER bits 4-7, FCR bits 4-5, and MCR bits 5-7. Reset Source: mod_g_arstn |
| 3:0 | SW_FLOW_CONTROL | R/W | 0h | Combinations of Software flow control can be selected by programming bit 3 - bit 0. See Software Flow Control Options Reset Source: mod_g_arstn |