DSP features:
Note: Features are common to DSP0 and DSP1 unless otherwise specified
- 1.0 GHz at 0.85V and 850MHz at 0.75V
- C7x ISA and RISC-V G ISA extensions
- Vector DSP, 40 GFLOPS
- 256-bit vector width
- DSP0 Only: Deep-learning Matrix Multiply Accelerator Version 2F (MMA2F) with floating point support
- L1 memory architecture
- 32KB I-cache
- 64KB D-cache
- L2 memory architecture
- 2.25 MB L2 with ECC protection on L2 SRAM
- 2.25MB is managed as 2MB segment named "Main" and a 256KB segment named "Auxiliary"
- Continuous L2 memory view
- Unified Memory Controller (UMC) facilitates L2 SRAM accesses from CPU and SOC (DMAs) as well as EMIF accesses from CPU.
- DRU (DMA engine) integrated that facilitates data transfer between L2 and system memories
- Event bus interfaces integrates with SOC DMS
- Tightly couples with C7x/MMA (DRU is not available for use when the C7x/MMA is disabled) and indirect predictor
- Full ECC support with RMW
- Interrupts
- Local event controller (CLEC) integrated within CorePac for routing and handling of DRU interrupts, CPU generated IPC events to SOC, interrupts coming from SOC
- Security
- Support for C7x Authenticated Boot. Security is in-context during boot to facilitate the authentication and loading of the C7x image.
- The C7x L2 SRAM (UMC) should not be used for storing security content as there is no protection of UMC memory from C7x itself. In a threat scenario, the C7x can be activated if in reset to execute malicious code to access data in UMC thereby defeating a protection for security data in UMC.
- No security should be inferred from DRU as this IP is out of scope for security.
- TrustZone debug controls (DBGEN, NIDEN, SPIDEN, SPNIDEN) are supported
- C7x data and configuration paths are not in-scope from security standpoint
- SOC shall support overriding the credentials (secure, priv-id) of all IP initiator ports. (e.g. via ISC)
- Safety
- Support for reporting safety errors to SOC via interrupt
- Debug
- Independent debug interface supporting access to embedded features
- Debug features include: Core debug, Advanced Event Triggering, Trace, CTSETs, and an embedded CP Tracer Aggregator with bus probes on internal memory interfaces
- Power Management
- Support for granular gated clock domains to support low power modes and to support memory interface utilization while IP disabled.
- Advanced SOC Integration
- Dedicated PLL for full flexibility in performance and power trade-offs
- Provides full asynchronous frequency independence between C7x and all other cores and Peripherals
- Dedicated windowed watchdog timer per core