SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | Dependencies |
|---|---|---|---|---|---|---|---|
| SPINLOCK0 | MAIN_PSC0 | GP_CORE | LPSC_SMS_COM | 14 | ON | YES | LPSC_MAIN_ALWAYSON |
| Module Instance | Source | Description |
|---|---|---|
| SPINLOCK0 | MAIN_PSC0 | SPINLOCK0 reset |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| N/A | N/A | N/A | N/A | N/A | N/A |
| Module Instance | Module Clock Input | Source Clock Signal | Source Control Register | Description |
|---|---|---|---|---|
| SPINLOCK0 | VBUS_FCLK | MAIN_PLL15_HSDIV0_CLKOUT/2 | SPINLOCK0 clock. This clock is used for all interface and functional operations |