SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Counter Timer Control Register 18
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| Instance Name | Physical Address |
|---|---|
| C7X256V1_DEBUG | 0007 3800 8A48h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| WDRESET | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| INPSEL | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| MODESEL | FILTER | DBG_TRIG_STAT | WDMODE | RESTART | DBG | INT | |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHNSDW | OVRFLW | RESERVED | DURMODE | CHAIN | RESET | ENBL | |
| R/W | R/W | R | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | WDRESET | R/W | 0h | WD reset event input selector. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function |
| 23:16 | INPSEL | R/W | 0h | Counter Timer input selection. For WD mode it is the start event selector |
| 15:14 | MODESEL | R/W | 0h | Counter is in duration or occurrence mode. Only writable by debug accesses |
| 13 | FILTER | R/W | 0h | Use associated operating mode filter in CTMODEFILTERn |
| 12 | DBG_TRIG_STAT | R/W | 0h | Debug event triggered. Write 1 will clear this bit. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function |
| 11 | WDMODE | R/W | 0h | WD Timer mode selection. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function |
| 10 | RESTART | R/W | 0h | Restart the timer after an interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function |
| 9 | DBG | R/W | 0h | Signal debug logic on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function |
| 8 | INT | R/W | 0h | Generate interrupt on interval match. Only available for modules capable of timer and counter functions. This bit is reserved (read only) for counter registers which are only counter function |
| 7 | CHNSDW | R/W | 0h | Counter has a shadow register for chain reads. Only valid on counters with an even number index |
| 6 | OVRFLW | R/W | 0h | Counter is in duration or occurrence mode |
| 5:4 | RESERVED | R | 0h | Reserved, returns 0 |
| 3 | DURMODE | R/W | 0h | Counter is in duration or occurrence mode |
| 2 | CHAIN | R/W | 0h | Counter is chained to an adjacent counter |
| 1 | RESET | R/W | 0h | Counter reset control |
| 0 | ENBL | R/W | 0h | Counter enable control |