SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register triggers a counter reload of timer by writing any value in it
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| TIMER0 | 0240 0044h |
| TIMER1 | 0241 0044h |
| TIMER2 | 0242 0044h |
| TIMER3 | 0243 0044h |
| TIMER4 | 0244 0044h |
| TIMER5 | 0245 0044h |
| TIMER6 | 0246 0044h |
| TIMER7 | 0247 0044h |
| TIMER8 | 0248 0044h |
| TIMER9 | 0249 0044h |
| TIMER10 | 024A 0044h |
| TIMER11 | 024B 0044h |
| TIMER12 | 024C 0044h |
| TIMER13 | 024D 0044h |
| TIMER14 | 024E 0044h |
| TIMER15 | 024F 0044h |
| WKUP_TIMER0 | 2B10 0044h |
| WKUP_TIMER1 | 2B11 0044h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TTRG_VLAUE | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TTRG_VLAUE | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TTRG_VLAUE | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TTRG_VLAUE | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | TTRG_VLAUE | R/W | 0h | The value of the trigger register. During reads, it always return 0xFFFF_FFFF Reset Source: mod_g_rst_n |