SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Map and routing register
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| Instance Name | Physical Address |
|---|---|
| C7X256V1_CLEC | 7D28 0000h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| S | ESE | RSVD3 | EVTPF | IS_LVL | |||
| R/W | R/W | R | R | R/W | |||
| 0h | 0h | 0h | 0h | 1h | |||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSVD2 | RTMAP | ||||||
| R | R/W | ||||||
| 0h | 1h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| EXT_EVTNUM | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD0 | C7X_EVTNUM | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | S | R/W | 0h | MRR.S - reserved, not used for AM62A since CPU doesn't support secure mode Reset Source: mod_g_rst_n |
| 30 | ESE | R/W | 0h | MRR.ESE - Event-Send enable. Controls whether CLEC sends this event when ESR is written or Event occurred on interrupt line Reset Source: mod_g_rst_n |
| 29:26 | RSVD3 | R | 0h | Reserved Reset Source: mod_g_rst_n |
| 25 | EVTPF | R | 0h | MRR.EPF - same value as EFR, read only pending status of all events regardless of they are enabled or disabled, for pulse events this flag is cleared as soon as event is sent, for level events this flag is cleared when input event is deasserted, writing 1 to ECR_n register also clears this bit in case of pending pulse event Reset Source: mod_g_rst_n |
| 24 | IS_LVL | R/W | 1h | MRR.IS_LVL - Indicate that input event is level or pulse, event handling is different based on whether event is level or pulse Reset Source: mod_g_rst_n |
| 23:22 | RSVD2 | R | 0h | Reserved Reset Source: mod_g_rst_n |
| 21:16 | RTMAP | R/W | 1h | MRR.RTMAP - If Bit [16] = 1 Send to None, If Bit [17] = 1 and bit [16] = 0 Send to System, If [16] = 0 and [17] = 0 send to [21:18] Corepac encoded value - value 1 and 0xF are valid since there is only one CPU Reset Source: mod_g_rst_n |
| 15:8 | EXT_EVTNUM | R/W | 0h | MRR.EXT_EVTNUM - encoded external event number, event 0- 63 SOC events, 64-95 DRU events, event 128 ARM event others are reserved for AM62A Reset Source: mod_g_rst_n |
| 7:6 | RSVD0 | R | 0h | Reserved Reset Source: mod_g_rst_n |
| 5:0 | C7X_EVTNUM | R/W | 0h | MRR.C7x_EVTNUM - C7x event number to send when this event is triggered Reset Source: mod_g_rst_n |