- Configure Clock Zones:
- Program Input Clock Zone Clock Source and Loop Setup:
- ASRC_ICKZCTRL_0[3-0]
INPUT_CLOCK_ZONE_CLOCK_SOURCE_SELECT register bitfield
- ASRC_ICKZCTRL_0[16-9] LOOP_SETUP register
bitfield
- Program Output Clock Zone Clock Source and Loop Setup
- ASRC_OCKZCTRL_0[3-0]
OUTPUT_CLOCK_ZONE_CLOCK_SOURCE_SELECT register bitfield
- ASRC_OCKZCTRL_0[16-9] LOOP_SETUP register
bitfield
- Program Clock Zone 0 divider and Clock Zone 1 divider values (optional step, required if ASRC module dividers are being used):
- ASRC_ICKDIV[13-0] CLOCK_ZONE0_DIVIDE
- ASRC_ICKDIV[29-16] CLOCK_ZONE1_DIVIDE
- ASRC_OCKDIV[13-0] CLOCK_ZONE0_DIVIDE
- ASRC_OCKDIV[29-16] CLOCK_ZONE1_DIVIDE
- Program Clock Zone 0 divider enable and Clock Zone 1 divider enable (optional step, required if ASRC module dividers are being used):
- ASRC_ICKDIV[14] CLOCK_ZONE0_DIVIDE_EN
- ASRC_ICKDIV[30] CLOCK_ZONE1_DIVIDE_EN
- ASRC_OCKDIV[14] CLOCK_ZONE0_DIVIDE_EN
- ASRC_OCKDIV[30] CLOCK_ZONE1_DIVIDE_EN
- Program INFIFO threshold and OUTFIFO threshold values:
- ASRC_SRCFFCTRL_0[7-0] INFIFO_THRESHOLD
- ASRC_SRCFFCTRL_0[23-16] OUTFIFO_THRESHOLD
- Program Output Word Length, Group Delay, De-emphasis Mode, Attenuation, Direct Down Sample, Mute, Dither Enable, Output Clock Zone Select and Input Clock Zone Select:
- ASRC_SRCCTRL_0[29-28] OUTPUT_WORD_LENGTH
- ASRC_SRCCTRL_0[27-26] GROUP_DELAY
- ASRC_SRCCTRL_0[25-24] DE_EMPHASIS_MODE
- ASRC_SRCCTRL_0[23-16] ATTENUATION
- ASRC_SRCCTRL_0[10] DIRECT_DOWN_SAMPLE
- ASRC_SRCCTRL_0[9] MUTE
- ASRC_SRCCTRL_0[8] DITHER_ENABLE
- ASRC_SRCCTRL_0[7-6] INPUT_WORD_LENGTH
- ASRC_SRCCTRL_0[5-3] OUTPUT_CLOCK_ZONE_SELECT
- ASRC_SRCCTRL_0[2-0] INPUT_CLOCK_ZONE_SELECT
- Program Data Alignment Disable (optional step, if desired):
- ASRC_SYSCONFIG[1] DATA_FORMAT_DISABLE
- Program Channel Enable:
- ASRC_SRCCTRL_0[31-30] CHANNEL_ENABLE
- Program DMA transfers:
- Once the INFIFO_EVT event is triggered, a maximum
block of ASRC_SRCFFCTRL_0[7-0] INFIFO_THRESHOLD audio samples can be
written to the data register. If OUTFIFO_EVT event is triggered, then
ASRC_SRCFFCTRL_0[23-16] OUTFIFO_THRESHOLD samples can be read from
output data register. Events will not be triggered until Input Clock
Recovery Loop and Output Clock Recovery Loop are settled. For this SW
must check the status of [8] SETTLE bit in ASRC_ICKZCTRL_0 and
ASRC_OCKZCTRL_0 registers, respectively.
The typical time that for an ASRC clock rate estimator to settle is proportionate to the clock rate that is input to the rate estimator. The typical setting time in ms is approximately 8850 / sample rate in kHz. A 192 kHz clock will typically settle in 46 ms.