SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Transmit packets are NOT modified during switch egress when the VLAN_AWARE bit in the CPSW3_CONTROL_REG register is cleared to 0h. This means that the switch is not in VLAN-aware mode.
The next three sections cover transmit processing when the switch is in VLAN-aware mode for different packet types. The Gigagibit Ethernet switch is in VLAN-aware mode when the VLAN_AWARE bit is set in the CPSW3_CONTROL_REG register. While in VLAN-aware mode, VLAN is added, removed, or replaced according to the type of packet as well as the CPSW3_CPSW_NU_ALE_ALE_UVLAN_UNTAG[1-0] UVLAN_FORCE_UNTAGGED_EGRESS bit in the packet header as explained below.