The L1P cache controller supports a fixed cache size of 32KB. The purpose of the L1P cache is to maximize performance of the code execution. L1P cache is necessary to facilitate fetching program code at a fast clock rate in order to maintain a large system memory. The cache is responsible for hiding the latency associated with executing code from the slower system memory.
The L1P memory system provides the following key features:
- L1 program memory controller (PMC) with 32KB L1P memory, all cache (no support for L1P SRAM)
- L1P cache
- 4-way set associative
- 64-byte line size
- Virtually indexed, virtually tagged (48-bit virtual address)
- Auto-prefetching on L1P misses from L2
- Capability to queue multiple fetch packet requests (64 bytes) to UMC to enable deeper prefetch in program pipeline
- Parity protection on Data and Tag rams with 1-bit error detection
- Data RAM parity protection is on instruction width granularity with 1 parity bit every 32 bits
- Auto-Invalidate and Re-Fetch on errors in TAG RAM
- Single cycle cache invalidates with support for three modes
- Virtual to Physical addressin on misses
- Extended Control Register (ECR) Access