SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
CRC Interrupt Status Register
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| Instance Name | Physical Address |
|---|---|
| MCRC64_0 | 3030 0028h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | CH4_TIME_OUT | CH4_UNDER | CH4_OVER | CH4_CRC_FAIL | CH4_CCIT | ||
| NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | CH3_TIME_OUT | CH3_UNDER | CH3_OVER | CH3_CRC_FAIL | CH3_CCIT | ||
| NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | CH2_TIME_OUT | CH2_UNDER | CH2_OVER | CH2_CRC_FAIL | CH2_CCIT | ||
| NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CH1_TIME_OUT | CH1_UNDER | CH1_OVER | CH1_CRC_FAIL | CH1_CCIT | ||
| NONE | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | RESERVED | NONE | 0h | Reserved |
| 28 | CH4_TIME_OUT | R/W1TC | 0h | Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active |
| 27 | CH4_UNDER | R/W1TC | 0h | Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active |
| 26 | CH4_OVER | R/W1TC | 0h | Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active |
| 25 | CH4_CRC_FAIL | R/W1TC | 0h | Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active |
| 24 | CH4_CCIT | R/W1TC | 0h | Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern compression complete interrupt is active |
| 23:21 | RESERVED | NONE | 0h | Reserved |
| 20 | CH3_TIME_OUT | R/W1TC | 0h | Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active |
| 19 | CH3_UNDER | R/W1TC | 0h | Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active |
| 18 | CH3_OVER | R/W1TC | 0h | Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active |
| 17 | CH3_CRC_FAIL | R/W1TC | 0h | Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active |
| 16 | CH3_CCIT | R/W1TC | 0h | Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern compression complete interrupt is active |
| 15:13 | RESERVED | NONE | 0h | Reserved |
| 12 | CH2_TIME_OUT | R/W1TC | 0h | Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active |
| 11 | CH2_UNDER | R/W1TC | 0h | Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active |
| 10 | CH2_OVER | R/W1TC | 0h | Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active |
| 9 | CH2_CRC_FAIL | R/W1TC | 0h | Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active |
| 8 | CH2_CCIT | R/W1TC | 0h | Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern compression complete interrupt is active |
| 7:5 | RESERVED | NONE | 0h | Reserved |
| 4 | CH1_TIME_OUT | R/W1TC | 0h | Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active |
| 3 | CH1_UNDER | R/W1TC | 0h | Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active |
| 2 | CH1_OVER | R/W1TC | 0h | Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active |
| 1 | CH1_CRC_FAIL | R/W1TC | 0h | Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active |
| 0 | CH1_CCIT | R/W1TC | 0h | Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern compression complete interrupt is active |