The ATL module is clocked by a functional clock (ATL_PCLK) and one interface clock (ATL_VCLK).
- The functional clock is used to generate control
signals depending on the internal configuration of the module. The ATL_PCLK
selection register mux for one of four compare clear registers (ATL0_PCLKMUX,
ATL1_PCLKMUX, ATL2_PCLKMUX, and ATL3_PCLKMUX) chooses the functional clock for
ATL_PCLK input to run error counting timers and to derive modulated ATCLK clock
outputs.
- ATL0_VCLK is used to trigger access to the ATL configuration interface through the CBASS0 Interconnect.
- A software reset register is provided to hold the
four ATL modules in reset while the AWS/BWS and ATL0_PCLK mux selections are set
and while the system-level clocking is configured. Software is required to
release the module from reset. Software must enable the bit [0] for one of four
compare clear registers (ATL0_SWEN, ATL1_SWEN, ATL2_SWEN, and ATL3_SWEN) to
enable the ATL. Each ATL in the device must be independently enabled.