SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR).
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| Instance Name | Physical Address |
|---|---|
| MCASP0 | 02B0 006Ch |
| MCASP1 | 02B1 006Ch |
| MCASP2 | 02B2 006Ch |
| MCASP3 | 02B3 006Ch |
| MCASP4 | 02B4 006Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED83 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED83 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RMOD | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RMOD | RESERVED82 | FRWID | RESERVED81 | FSRM | FSRP | ||
| R/W | R | R/W | R | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED83 | R | 0h | |
| 15:7 | RMOD | R/W | 0h | Receive frame sync mode select bits. 1FFh = Reserved from 181h to 1FFh. 0 Burst mode.
1 Reserved.
2 2-slot TDM (I2S mode) to 32-slot TDM from
2h to 20h.
33 Reserved from 21h to 17Fh.
384 384-slot TDM (external DIR IC inputting
384-slot DIR frames to McASP over I2S
interface).
385 Reserved from 181h to 1FFh. |
| 6:5 | RESERVED82 | R | 0h | |
| 4 | FRWID | R/W | 0h | Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period. 0 Single bit. 1 Single word. |
| 3:2 | RESERVED81 | R | 0h | |
| 1 | FSRM | R/W | 0h | Receive frame sync generation select bit. 0 Externally-generated receive frame sync. 1 Internally-generated receive frame sync. |
| 0 | FSRP | R/W | 0h | Receive frame sync polarity select bit. 0 A rising edge on receive frame sync (AFSR)
indicates the beginning of a frame.
1 A falling edge on receive frame sync (AFSR)
indicates the beginning of a frame. |