SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register gives the status of all the interrupts
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 0030h |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| ERROR_INTR | BOOT_COMPLETE | RCV_BOOT_ACK | RETUNING_EVENT | INTC | INTB | INTA | CARD_INTR |
| R | R/W1TC | R/W1TC | R | R | R | R | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CARD_REM | CARD_INS | BUF_RD_READY | BUF_WR_READY | DMA_INTERRUPT | BLK_GAP_EVENT | XFER_COMPLETE | CMD_COMPLETE |
| R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | ERROR_INTR | R | 0h |
If any of the bits in the Error Interrupt Status Register are set, then this bit is set. Therefore the HD can test for an error by checking this bit first.
In UHS-II mode is enabled, if any of the bits in the UHS-II Error Interrupt Status register are set, this bit is also set.
'0' No error
'1' Error
1 Error interrupt is generated 0 No Interrupt |
| 14 | BOOT_COMPLETE | R/W1TC | 0h |
This status is set if the boot operation gets terminated.
'0' Boot operation is not terminated
'1' Boot operation is terminated
1 Boot Terminate interrupt is generated 0 No Interrupt |
| 13 | RCV_BOOT_ACK | R/W1TC | 0h |
This status is set if the boot acknowledge is received from device.
'0' Boot ack not recieved
'1' Boot ack is recieved
1 Boot acknowledge is received 0 No Interrupt |
| 12 | RETUNING_EVENT | R | 0h | This status is set if Re-Tuning Request in the Present State register changes from 0 to 1. Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer [not large block count] can be completed without re-tuning.In UHS-II mode, this bit is not effective '0' Re-tuning not required '1' Re-tuning should be performed Reset Source: vbus_amod_g_rst_n |
| 11 | INTC | R | 0h | This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt factor. Reset Source: vbus_amod_g_rst_n |
| 10 | INTB | R | 0h | This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_B interrupt factor. Reset Source: vbus_amod_g_rst_n |
| 9 | INTA | R | 0h | This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_A interrupt factor. NOTE : INT_A, INT_B, and INT_C are to be implemented based on the Application Requirements. By default these are not implemented as there is no specific requirement from Customers. Reset Source: vbus_amod_g_rst_n |
| 8 | CARD_INTR | R | 0h |
When this status has been set and the Host Driver needs to start this interrupt service, Card Interrupt Status Enable in the Normal Interrupt Status Enable register may be set to 0 in order to clear the card interrupt status latched in the Host Controller and to stop driv-ing the interrupt signal to the Host System.After completion of the card interrupt service [It should reset interrupt factors in the SD card and the interrupt signal may not be asserted],set Card Interrupt Status Enable to 1 and start sampling the interrupt signal again.
Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt fac-tor.
[1] DAT[1] Interrupt Input in SD Mode
In 1-bit mode, the Host Controller shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt sig-nal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the SD card and the inter-rupt to the Host System. Interrupt detected by DAT[1] is supported when there is a card per slot. In case of UHS-I mode, switching time of Interrupt Period is relaxed for 2 clock cycles. Then Host Controller needs to delay start of interrupt sampling at least 2 clocks and should sample interrupt while Interrupt Period is sta-ble.
[2] DAT[2] Interrupt Input in UHS-II Mode
When Card Inserted in the Present State reg-ister and SD Bus Power for VDD1 in the Power Control register are set to 1, Host Con-troller configures DAT[2] as Interrupt Input and enables pull-up of DAT[2]. DAT[2] interrupt is asynchronous to RCLK, low level sensitive and 3.3V signal level. DAT[2] interrupt is masked by setting Card Interrupt Status Enable to 0 in the Normal Interrupt register.When either Card Inserted or SD Bus Power for VDD1 is set to 0, Host Controller sets DAT[2] to low. Only point to point connection is allowed between Host and Card.
[3] INT MSG in UHS-II Mode
INT MSG is enabled by setting INT MSG Enable in the UHS-II Device Select register. DAT[2] and INT MSG interrupt sources are ORed and indicated to Card Interrupt. If any bit in the UHS-II Device Interrupt Status regis- ter is set to 1, INT MSG interrupt is generated. INT MSG interrupt is cleared by writing a cor-respondent bit to 1 in the UHS-II Device Inter-rupt Status register. Masking DAT[2] interrupt also disables INT MSG interupt due to Card Interrupt Status Enable is set to 0. SDIO Ver-sion 4.00 does not support INT MSG.
'0' No Card Interrupt
'1' Generate Card Interrupt
1 Card interrupt is generated 0 No Interrupt |
| 7 | CARD_REM | R/W1TC | 0h |
This status is set if the Card Inserted in the Present State register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.
'0' Card State Stable or Debouncing
'1' Card Removed
1 Card removal interrupt is generated 0 No Interrupt |
| 6 | CARD_INS | R/W1TC | 0h |
This status is set if the Card Inserted in the Present State register changes from 0 to 1.When the HD writes this bit to 1 to clear this status the status of the Card Inserted in the Present State register should be confirmed. Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.
'0' Card State Stable or Debouncing
'1' Card Inserted
1 Card insertion interrupt is generated 0 No Interrupt |
| 5 | BUF_RD_READY | R/W1TC | 0h |
This status is set if the Buffer Read Enable changes from 0 to 1.
Buffer Read Ready is set to 1 for every CMD19 execution in tuning procedure.In UHS-II mode, this bit is set at FC [Flow Control] unit basis.
'0' Not ready to read buffer,
'1' Ready to read buffer
1 Buffer Read Ready interrupt is generated 0 No Interrupt |
| 4 | BUF_WR_READY | R/W1TC | 0h |
This status is set if the Buffer Write Enable changes from 0 to 1.In UHS-II mode, this bit is set at FC [Flow Control] unit basis.
'0' Not ready to write to buffer,
'1' Ready to write to buffer
1 Buffer Write Ready interrupt is generated 0 No Interrupt |
| 3 | DMA_INTERRUPT | R/W1TC | 0h |
This status is set if the HC detects the Host DMA Buffer Boundary in the Block Size regiser.
'0' No DMA Interrupt
'1' DMA Interrupt is generated
1 DMA interrupt is generated 0 No Interrupt |
| 2 | BLK_GAP_EVENT | R/W1TC | 0h |
If the Stop At Block Gap Request in the BlockGap Control Register is set, this bit is set.
Read Transaction:
This bit is set at the falling edge of the DAT Line Active Status [When the transaction is stopped at SD Bus timing. The Read Wait must be supported inorder to use this function].
Write Transaction:
This bit is set at the falling edge of Write Transfer Active Status [After getting CRC status at SD Bus timing].
In UHS-II mode, this bit is set at FC [Flow Control] unit basis.
'0' No Block Gap Event
'1' Transaction stopped at Block Gap
1 Block Gap Event is generated 0 No Interrupt |
| 1 | XFER_COMPLETE | R/W1TC | 0h |
This bit is set when a read / write transaction is completed.
SD Mode
Read Transaction:
This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which the Interrupt is generated. The first is when a data transfer is completed as specified by data length [After the last data has been read to the Host Sys- tem]. The second is when data has stopped at the block gap and completed the data transfer by setting the Stop At Block Gap Request in the Block Gap Control Register [After valid data has been read to the Host System].
Write Transaction:
This bit is set at the falling edge of the DAT Line Active Status. There are two cases in which the Interrupt is generated. The first is when the last data is written to the card as specified by data length and Busy signal is released. The second is when data transfers are stopped at the block gap by setting Stop At Block Gap Request in the Block Gap Control Register and data transfers completed. [After valid data is written to the SD card and the busy signal is released].
Note: Transfer Complete has higher priority than Data Time-out Error. If both bits are set to 1, the data transfer can be considered complete.
Note: While performing tuning procedure [Execute Tuning is set to 1], Transfer Complete is not set to 1
Command with Busy:
This bit is set when busy is de-asserted. Refer to DAT Line Active and Command Inhibit[DAT] in the Present State register.UHS-I mode While performing tuning procedure [Execute Tuning is set to 1], Transfer Complete is not set to 1.
'0' No Data Transfer Complete,
'1' Data Transfer Complete
UHS-II Mode
This interrupt is generated in following twocases:
[a] EBSY Completion [for EBSY supported commands] When EBSY Wait in the UHS-II Transfer Mode register is set to 1, this bit is set when EBSY packet has been received, and all valid data have been sent to system memory in case of read operation.
[b] Stop and Continue during DCMD Data Transfer When Stop At Block Gap Request in the Block Gap Control register is set to 1 and data transfer is stopped at the Flow Control.
Following is for both SD mode and UHS-II mode.
The table below shows that Transfer Com-plete has higher priority than Data Timeout Error. If both bits are set to 1, execution of a command can be considered to be completed.
1 - Command execution is completed
0 - Not complete
1 Transfer complete interrupt is generated 0 No Interrupt |
| 0 | CMD_COMPLETE | R/W1TC | 0h |
SD Mode
This bit is set when we get the end bit of the command response [Except Auto CMD12 and Auto CMD23]
Note: Command Time-out Error has higher priority than Command Complete. If both are set to 1, it can be considered that the response was not received correctly.
Version 4.00 defines response check function for R1 and R5. If Response Interrupt Disable in the Transfer Mode register is set to 1, gen-eration of this interrupt is prohibited regardless of Command Complete Signal Enable.
UHS-II Mode
If Response Interrupt Disable is set to 0 in the UHS-II Transfer Mode register, this interrupt is generated when response packet is received.If Response Interrupt Disable is set to 1 in the UHS-II Transfer Mode register, generation of this interrupt is prohibited regardless of Com-mand Complete Signal Enable.
'0' No Command Complete,
'1' Command Complete
1 Command complete interrupt is generated 0 No Interrupt |