SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
RTI Set/Status Interrupt Register
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| Instance Name | Physical Address |
|---|---|
| SMS0_RTI_1 | 4393 5080h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SETOVL1INT | SETOVL0INT | SETTBINT | ||||
| NONE | R/W1TS | R/W1TS | R/W1TS | ||||
| 0h | 0h | 0h | 0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SETDMA3 | SETDMA2 | SETDMA1 | SETDMA0 | |||
| NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SETINT3 | SETINT2 | SETINT1 | SETINT0 | |||
| NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:19 | RESERVED | NONE | 0h | Reserved |
| 18 | SETOVL1INT | R/W1TS | 0h | User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt Reset Source: sms_custom_rst_mod_g_rst_n |
| 17 | SETOVL0INT | R/W1TS | 0h | User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt Reset Source: sms_custom_rst_mod_g_rst_n |
| 16 | SETTBINT | R/W1TS | 0h | User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt Reset Source: sms_custom_rst_mod_g_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11 | SETDMA3 | R/W1TS | 0h | User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request Reset Source: sms_custom_rst_mod_g_rst_n |
| 10 | SETDMA2 | R/W1TS | 0h | User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request Reset Source: sms_custom_rst_mod_g_rst_n |
| 9 | SETDMA1 | R/W1TS | 0h | User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request Reset Source: sms_custom_rst_mod_g_rst_n |
| 8 | SETDMA0 | R/W1TS | 0h | User and privilege mode (read): 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable DMA request Reset Source: sms_custom_rst_mod_g_rst_n |
| 7:4 | RESERVED | NONE | 0h | Reserved |
| 3 | SETINT3 | R/W1TS | 0h | User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt Reset Source: sms_custom_rst_mod_g_rst_n |
| 2 | SETINT2 | R/W1TS | 0h | User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt Reset Source: sms_custom_rst_mod_g_rst_n |
| 1 | SETINT1 | R/W1TS | 0h | User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt Reset Source: sms_custom_rst_mod_g_rst_n |
| 0 | SETINT0 | R/W1TS | 0h | User and privilege mode (read): 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode (write): 0 = leaves the corresponding bit unchanged 1 = enable interrupt Reset Source: sms_custom_rst_mod_g_rst_n |