SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Global USB 2.0 ULPI PHY Vendor Control Register The application uses this register to access the PHY registers. This register is always implemented when the ULPI PHY Interface is enabled during coreConsultant configuration (parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3). For an ULPI PHY, the controller uses the ULPI interface for PHY register access. The application sets the Vendor Control register for PHY register access and times the PHY register access. The application polls the VStatus Done bit in this register for the completion of the PHY register access. In Device-only configurations, only one register is needed. In Host mode, per-port registers are implemented.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C280h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31_27 | DISUIPIDRVR | NEWREGREQ | VSTSDONE | ||||
| R | R | R | R | ||||
| 0h | 0h | 0h | 0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| VSTSBSY | REGWR | REGADDR | |||||
| R | R | R | |||||
| 0h | 0h | 0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| EXTREGADDR | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| REGDATA | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:27 | RESERVED_31_27 | R | 0h | Reserved |
| 26 | DISUIPIDRVR | R | 0h | DISUIPIDRVR Reset Source: rst_mod_g_rst_n |
| 25 | NEWREGREQ | R | 0h | New Register Request The application sets this bit for a new vendor control access. Setting this bit to 1 asserts the utmi_vcontrolload_n [1'b0] on the UTMI interface. Reset Source: rst_mod_g_rst_n |
| 24 | VSTSDONE | R | 0h | VSTSDONE Reset Source: rst_mod_g_rst_n |
| 23 | VSTSBSY | R | 0h | VSTSBSY Reset Source: rst_mod_g_rst_n |
| 22 | REGWR | R | 0h | Register Write The application sets this bit for register writes and clears it for register reads. Note: This bit is applicable for ULPI register read/write access only. Reset Source: rst_mod_g_rst_n |
| 21:16 | REGADDR | R | 0h | Register Address The 6-bit PHY register address for immediate PHY Register Set access. Set to 6'h2F for Extended PHY Register Set access. Note: These bits are applicable for ULPI only. Reset Source: rst_mod_g_rst_n |
| 15:8 | EXTREGADDR | R | 0h | EXTREGADDR Reset Source: rst_mod_g_rst_n |
| 7:0 | REGDATA | R | 0h | REGDATA Reset Source: rst_mod_g_rst_n |