SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Index | Default | Controllable | Dependencies |
|---|---|---|---|---|---|---|---|
| MLB0 | MAIN_PSC0 | GP_CORE | LPSC_MAIN_MLB | 40 | OFF | YES | LPSC_MAIN_IP0 |
| Module Instance | Source | Description |
|---|---|---|
| MLB0 | MAIN_PSC0 | MLB0 reset |
| Module Instance | Module Clock Input | Source Clock Signal | Source Control Register | Description |
|---|---|---|---|---|
| MLB0 | MLBSS_AMLB_CLK | MCU_TIEOFF0 | ||
| MLBSS_HCLK_CLK | MAIN_SYSCLK0/2 | |||
| MLBSS_PCLK_CLK | MAIN_SYSCLK0/2 | |||
| MLBSS_SCLK_CLK | MAIN_SYSCLK0/2 |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| MLB0 | MLB0_mlbss_ecc_corr_lvl_0 | ESM0_esm_lvl_event_IN_77 | ESM0 | MLB0 interrupt request | level |
| MLB0_mlbss_ecc_uncorr_lvl_0 | ESM0_esm_lvl_event_IN_78 | ESM0 | MLB0 interrupt request | level | |
| MLB0_mlbss_mlb_ahb_int_[1:0] | C7X256V0_CLEC_gic_spi_IN_61 | C7X256V0_CLEC | MLB0 interrupt request | level | |
| C7X256V0_CLEC_gic_spi_IN_62 | C7X256V0_CLEC | MLB0 interrupt request | level | ||
| C7X256V1_CLEC_gic_spi_IN_61 | C7X256V1_CLEC | MLB0 interrupt request | level | ||
| C7X256V1_CLEC_gic_spi_IN_62 | C7X256V1_CLEC | MLB0 interrupt request | level | ||
| R5FSS0_CORE0_intr_IN_61 | R5FSS0_CORE0 | MLB0 interrupt request | level | ||
| R5FSS0_CORE0_intr_IN_62 | R5FSS0_CORE0 | MLB0 interrupt request | level | ||
| R5FSS0_CORE1_intr_IN_61 | R5FSS0_CORE1 | MLB0 interrupt request | level | ||
| R5FSS0_CORE1_intr_IN_62 | R5FSS0_CORE1 | MLB0 interrupt request | level | ||
| R5FSS1_CORE0_intr_IN_61 | R5FSS1_CORE0 | MLB0 interrupt request | level | ||
| R5FSS1_CORE0_intr_IN_62 | R5FSS1_CORE0 | MLB0 interrupt request | level | ||
| R5FSS1_CORE1_intr_IN_61 | R5FSS1_CORE1 | MLB0 interrupt request | level | ||
| R5FSS1_CORE1_intr_IN_62 | R5FSS1_CORE1 | MLB0 interrupt request | level | ||
| MLB0_mlbss_mlb_int_0 | C7X256V0_CLEC_gic_spi_IN_60 | C7X256V0_CLEC | MLB0 interrupt request | level | |
| C7X256V1_CLEC_gic_spi_IN_60 | C7X256V1_CLEC | MLB0 interrupt request | level | ||
| R5FSS0_CORE0_intr_IN_60 | R5FSS0_CORE0 | MLB0 interrupt request | level | ||
| R5FSS0_CORE1_intr_IN_60 | R5FSS0_CORE1 | MLB0 interrupt request | level | ||
| R5FSS1_CORE0_intr_IN_60 | R5FSS1_CORE0 | MLB0 interrupt request | level | ||
| R5FSS1_CORE1_intr_IN_60 | R5FSS1_CORE1 | MLB0 interrupt request | level |