SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Watchdog Key Register
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| Instance Name | Physical Address |
|---|---|
| SMS0_RTI_1 | 4393 509Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| WDKEY | |||||||
| R/W | |||||||
| A35Ch | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| WDKEY | |||||||
| R/W | |||||||
| A35Ch | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15:0 | WDKEY | R/W | A35Ch | User and privilege mode reads are indeterminate. Privilege mode (write): A write of 0xE51A followed by 0xA35C in two separate write operations defines the Key Sequence and discharges the watchdog capacitor. This also causes the upper 12 bits of the DWD down counter to be reloaded with the contents of the DWD preload register and the lower 13 bits to become all 1's. Writing any other value causes a digital watchdog reset, as shown in Table 1-3. Note: Register write access time precaution The user has to take into account that the write to the register takes 3 VCLK cycle. This needs to be considered for the AWD/DWD expiration calculation. Table 2. Example of a WDKEY sequence Value written to Step WDKEY Result 1 0x0A35C No Action 2 0x0A35C No Action 3 0x0E51A WDKEY is enabled for reset by next 0x0A35C 4 0x0E51A WDKEY is enabled for reset by next 0x0A35C 5 0x0E51A WDKEY is enabled for reset by next 0x0A35C 6 0x0A35C Watchdog is reset 7 0x0A35C No Action 8 0x0E51A WDKEY is enabled for reset by next 0x0A35C 9 0x0A35C Watchdog is reset 10 0x0E51A WDKEY is enabled for reset by next 0x0A35C 11 0x02345 System reset; incorrect value written to WDKEY Reset Source: sms_custom_rst_mod_g_rst_n |