SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This is a software Top Level domain warm reset defined in Top Level domain CTRLMMR.
MCU CTRLMMR defines a 4-bit field, SW_MCU_WARMRST[11:8] (MCU_CTRL_MMR_CFG0_RST_CTRL Register) for generating a software warm reset in the MCU domain (SW_MCU_WARMRSTz).
When SW_MCU_WARMRST[11:8] field is set to “0110”, MCU warm reset is active (SW_MCU_WARMRSTz = LOW).
When SW_MCU_WARMRST[11:8] is set to any other value, MCU warm reset is inactive (SW_MCU_WARMRSTz = HIGH).
This bit field is reset to “1111” (Inactive State) by default.
This software reset is equivalent to MCU_RESETz warm reset signal (MCU_RESETz HW Pin) functionality.
All modules in the Top Level domain are reset except for MCU domain CTRLMMR bits which are reset only on MCU_PORz.
IOs are not affected.
R5FSS processor is reset.
When MCU_RESETz is de-asserted, the MCU domain needs to be reconfigured by the R5FSS (secondary boot loader) in the MAIN domain.
All modules in the MAIN domain are reset except for CTRLMMR bits which are reset only on PORz.
IOs are not affected.
All processor cores are reset (SMS, and R5FSS).
When MCU_RESETz is de-asserted, the device goes through full boot. The reason for this reset is captured in CTRLMMR reset source register MCU_CTRL RST_SRC
During device boot-up, the R5FSS (secondary boot loader) will read the CTRLMMR reset status and MCU ACTIVE MAGIC WORD and reconfigure the domains and R5FSS processor accordingly.