SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Register containing low power mode status bits. The status bits are set when the corresponding wakeup event happens and the corresponding enable in WAKEUP_CONFIG MMR is set. In addition, these bits are only set if clockstop request from PSC is active in order to ensure that these are captured only during low power mode and not during regular operation. These bits can only be set by hardware and once set, they can only be cleared by software by setting wakeup_stat_clear field.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 0F90 0034h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSVD1 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSVD1 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD1 | OVERCURRENT_N_WAKEUP_CURRENT | OVERCURRENT_N_WAKEUP_PREV | LINESTATE_WAKEUP_CURRENT | LINESTATE_WAKEUP_PREV | SESSVALID_WAKEUP_CURRENT | ||
| R | R | R | R | R | R | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SESSVALID_WAKEUP_PREV | VBUSVALID_WAKEUP_CURRENT | VBUSVALID_WAKEUP_PREV | OVERCURRENT_N_WAKEUP_STAT | LINESTATE_WAKEUP_STAT | SESSVALID_WAKEUP_STAT | VBUSVALID_WAKEUP_STAT | WAKEUP_STAT_CLEAR |
| R | R | R | R | R | R | R | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:15 | RSVD1 | R | 0h | Reserved bits Reset Source: cfg_srst_n |
| 14 | OVERCURRENT_N_WAKEUP_CURRENT | R | 0h | overcurrent_n current value during wakeup event Reset Source: cfg_srst_n |
| 13 | OVERCURRENT_N_WAKEUP_PREV | R | 0h | overcurrent_n previous value during wakeup event Reset Source: cfg_srst_n |
| 12:11 | LINESTATE_WAKEUP_CURRENT | R | 0h | Linestate current value during wakeup event Reset Source: cfg_srst_n |
| 10:9 | LINESTATE_WAKEUP_PREV | R | 0h | Linestate previous value during wakeup event Reset Source: cfg_srst_n |
| 8 | SESSVALID_WAKEUP_CURRENT | R | 0h | SESSVALID current value during wakeup event Reset Source: cfg_srst_n |
| 7 | SESSVALID_WAKEUP_PREV | R | 0h | SESSVALID previous value during wakeup event Reset Source: cfg_srst_n |
| 6 | VBUSVALID_WAKEUP_CURRENT | R | 0h | VBUSVALID current value during wakeup event Reset Source: cfg_srst_n |
| 5 | VBUSVALID_WAKEUP_PREV | R | 0h | VBUSVALID previous value during wakeup event Reset Source: cfg_srst_n |
| 4 | OVERCURRENT_N_WAKEUP_STAT | R | 0h | overcurrent_n event wakeup status. This is only looking for change on port_overcurrent_n input and does not include overcurrent MMR. This is because wakeup is required only for a port event and for any software write to happen, SOC should already have been awake. Also SOC may be tying off port_overcurrent_n, so this event may never trigger. Reset Source: cfg_srst_n |
| 3 | LINESTATE_WAKEUP_STAT | R | 0h | linestate event wakeup status Reset Source: cfg_srst_n |
| 2 | SESSVALID_WAKEUP_STAT | R | 0h | SESSVALID event wakeup status Reset Source: cfg_srst_n |
| 1 | VBUSVALID_WAKEUP_STAT | R | 0h | VBUSVALID event wakeup status Reset Source: cfg_srst_n |
| 0 | WAKEUP_STAT_CLEAR | R/W1TC | 0h | Clears all the *_wakeup_stat bits in this register Reset Source: cfg_srst_n |