SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Power Sleep Controller (PSC) is a control component to manage the power domain and module’s clock and reset transition. Each PSC module contains multiple power domains, within each power domain, it can contain multiple LPSC. Each LPSC can be used to manage the one or multiple module’s reset and clock stop status, see PSC Architecture.
Each power domain has a unique index, starting from number 0. The power domain 0 is a special power domain, which is always on. The status of power domain 0 can’t be changed after the device is out of reset.
Each power domain can have one or more Local Power Sleep Control (LPSC). Each LPSC in the same PSC has a unique index value as well. LPSC 0 is special, which user can’t change its status. LPSC 0 is always set to be enabled after the device is out of reset.
One LPSC can be used to control the reset and clock status for one or more modules. Some of the LPSC can be used to provide local reset function for the processors. LPSC can also be used to manage the clock stop interface for the interfaces between two interconnect IPs. This is mainly used for providing isolation features required by some special features such as security isolation, functional safety isolation or reset isolation between different parts of the SoC.