SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Structural Parameters 3 Register For register definitions, refer to the xHCI specification.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 000Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| U2_DEVICE_EXIT_LAT | |||||||
| R | |||||||
| 7FFh | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| U2_DEVICE_EXIT_LAT | |||||||
| R | |||||||
| 7FFh | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_15_8 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| U1_DEVICE_EXIT_LAT | |||||||
| R | |||||||
| Ah | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | U2_DEVICE_EXIT_LAT | R | 7FFh | U2 Device Exit Latency Reset Source: rst_mod_g_rst_n |
| 15:8 | RESERVED_15_8 | R | 0h | Reserved |
| 7:0 | U1_DEVICE_EXIT_LAT | R | Ah | U1 Device Exit Latency Reset Source: rst_mod_g_rst_n |