SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
RTI Capture Up Counter 1 Register
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| Instance Name | Physical Address |
|---|---|
| SMS0_RTI_1 | 4393 5044h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CAUC1 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CAUC1 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CAUC1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CAUC1 | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | CAUC1 | R | 0h | This registers captures the current value of the Up Counter 1 when a event occurs, controlled by the external capture control block. The read sequence has to be the same as with Up Counter 1 and Free Running Counter 1. So the RTICAFRC1 register has to be read first, before the RTICAUC1 register is read. This sequence ensures that the value of the RTICAUC0 register is the corresponding value to the RTICAFRC0 register, even if another capture event happens in between the two reads. User and privilege mode (read): value of Up Counter 1 on a capture event Reset Source: sms_custom_rst_mod_g_rst_n |