SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Time-Base Control Register
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| Instance Name | Physical Address |
|---|---|
| EPWM0 | 2300 0000h |
| EPWM1 | 2301 0000h |
| EPWM2 | 2302 0000h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| FREE_SOFT | PHSDIR | CLKDIV | HSPCLKDIV | ||||
| R/W | R/W | R/W | R/W | ||||
| 0h | 0h | 0h | 1h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HSPCLKDIV | SWFSYNC | SYNCOSEL | PRDLD | PHSEN | CTRMODE | ||
| R/W | R/W | R/W | R/W | R/W | R/W | ||
| 1h | 0h | 0h | 0h | 0h | 3h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:14 | FREE_SOFT | R/W | 0h | Emulation Mode Bits These bits select the behavior of the ePWM time-base counter during emulation events: 0h Stop after the next time-base counter
increment or decrement
1h Stop when counter completes a whole cycle
(a) Up-count mode: stop when the time-base
counter = period (EPWM_TBCNT[15-0] TBCNT =
EPWM_TBPRD[15-0] TBPRD). (b) Down-count
mode: stop when the time-base counter =
0000 (EPWM_TBCNT[15-0] TBCNT = 0000h)
2h Free run
3h Free run |
| 13 | PHSDIR | R/W | 0h | Phase Direction Bit This bit is only used when the time-base counter is configured in the up-down-count mode The PHSDIR bit indicates the direction the time-base counter [TBCNT] will count after a synchronization event occurs and a new phase value is loaded from the phase [TBPHS] register This is irrespective of the direction of the counter before the synchronization event In the up-count and down-count modes this bit is ignored 0h Count down after the synchronization event 1h Count up after the synchronization event |
| 12:10 | CLKDIV | R/W | 0h | Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] 0h /1 (default on reset) 1h /2 2h /4 3h /8 4h /16 5h /32 6h /64 7h /128 |
| 9:7 | HSPCLKDIV | R/W | 1h | High-Speed Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value TBCLK = SYSCLKOUT/[HSPCLKDIV - CLKDIV] This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager [EV] peripheral 0h /1 1h /2 (default on reset) 2h /4 3h /6 4h /8 5h /10 6h /12 7h /14 |
| 6 | SWFSYNC | R/W | 0h | Software Forced Synchronization Pulse 0h Writing a 0h 1h Writing a 1h |
| 5:4 | SYNCOSEL | R/W | 0h | Synchronization Output Select These bits select the source of the EPWMxSYNCO signal 0h EPWMxSYNC
1h TBCNT = 0: Time-base counter equal to zero
(EPWM_TBCNT[15-0] TBCNT = 0000h)
2h TBCNT = CMPB: Time-base counter equal to
counter-compare B (EPWM_TBCNT[15-0] TBCNT =
EPWM_CMPB[15-0] CMPB)
3h Disable EPWMxSYNCO signal |
| 3 | PRDLD | R/W | 0h | Active Period Register Load From Shadow Register Select 0h The period register (EPWM_TBPRD) is loaded
from its shadow register when the time-base
counter, EPWM_TBCNT[15-0] TBCNT, is equal
to zero. A write or read to the EPWM_TBPRD
register accesses the shadow register.
1h Load the EPWM_TBPRD register immediately
without using a shadow register. A write or
read to the EPWM_TBPRD register directly
accesses the active register. |
| 2 | PHSEN | R/W | 0h | Counter Register Load From Phase Register Enable 0h Do not load the time-base counter
(EPWM_TBCNT) from the time-base phase
register (EPWM_TBPHS)
1h Load the time-base counter with the phase
register when an EPWMxSYNCI input signal
occurs or when a software synchronization
is forced by the SWFSYNC bit. |
| 1:0 | CTRMODE | R/W | 3h | Counter Mode The time-base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter, the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change These bits set the time-base counter mode of operation as follows: 0h Up-count mode
1h Down-count mode
2h Up-down-count mode
3h Stop-freeze counter operation (default on
reset) |