SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This device supports an Arm CoreSight compliant four-channel programmable on-chip Cross Triggering network. In addition to the four-channel on-chip network, this device implements two channels of product level triggering via the EMU0 and EMU1 device pins.
Conceptually, each channel of Cross Triggering can be viewed as mapping of a user-defined set of events to a user-defined set of actions, where the occurrence of any event in the set-of-events results in the generation of the set-of-actions. The below table provides a domain-level summary of the supported events and actions.
| Domain | Events | Actions |
|---|---|---|
| Product-Level | Zero detected on EMU0 input pin | EMU0 output pin driven to Zero |
| Zero detected on EMU1 input pin | EMU1 output pin driven to Zero | |
| SoC Debug | TBR Acquisition Complete | TPIU insert trigger packet |
| TBR Embedded buffer is full | TPIU start flush process | |
| System reset asserted | TBR insert trigger packet | |
| Bus Probe-n match | TBR start flush process | |
| STM write to a TRIG location | Bus Probe-n Start | |
|
STM write to a trigger-enabled stimulus port |
Bus Probe-n Stop | |
| MAIN_R5F | MAIN_R5F has halted | MAIN_R5F – halt request |
| PMU generated interrupt | MAIN_R5F – resume request | |
| ETM Trigger outputs | ETM Trigger inputs | |
| WKUP_R5F | WKUP_R5F has halted | WKUP_R5F – halt request |
| PMU generated interrupt | WKUP_R5F – resume request | |
| ETM Trigger outputs | ETM Trigger inputs | |
| C7XSS0/C7XSS1 | C7XSS core has halted | C7XSS core – halt request |
| AET Trigger output | C7XSS core – resume reques | |
| -- | AET Trigger input |