SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
When the EMUDBG signal is set for a RAT transaction the region address translation occurs.
When the EMUDBG signal is set for a any transaction, the FLC pauses the copy function if copying until an non EMUDBG transaction is seen. This simulate what happens if user is single stepping the processor. The dbgsusp port also pauses the FLC without requiring a transaction. The FLC resumes after dbgsusp port goes back low.
When the EMUDBG signal is set for a RL2 transaction, the cache state is maintained. That is, EMUDBG request won't allocate a cache line in the case of a 'miss', or update the LRU state in the case of a 'hit'. But if the address is within the cache, the EMUDBG request gets the data from the remote cache data storage memory.