SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
ESM modules in the Top Level domain and Main domains can be configured to trigger ESM error pin on critical error conditions. MCU_ESM's reset is triggered when the high prioty interrupt or configuration error interrupts is asserted. Similarly, MAIN_ESM's reset is triggered when the MCU ESM High priority interrupt on configuration error interrupt is asserted. These ESM resets can be enabled by configuring either of these MCU MMR CTRL MCU_ESM_ERROR_RST_ENz and WKUP MMRT CTRL MAIN_ESM_ERROR_RST_ENz MMR bits to 0.
The MCU_ERRORn pin indicates the MCU domain ESM status. The output signals to an external agent that it needs to (or may need to) intervene because of an error. The Error Pin Output is active Low or PWM, based on the ESM Error Pin Control register pwm_en field. The field should only be modified when the ESM is disabled, based on the Global Enable register.
While in Power-On-Reset, the Error Pin is active (assert low). SoC drives a Low via a weak internal pull-down. After Power-On-Reset condition is removed, ESM will drive the Error Pin. During a warm reset, the state of the error pin is unchanged.
When MCU_ERRORn output pin is configured to operate in a level mode, a LOW indicates the MCU_ESM module has registers as error. A HIGH indicates that there are no MCU_ESM errors. When the pin is configured to operate in PWM mode, no error is indicated by continuous toggle according to programmable MMR with for high and low periods. When an error occurs, the error pin stops toggling and remain constant until the error is clear. An external device that is detecting the PWM toggles can identify the error if the pin stops toggling. The periods should be programmed such that they fit within the expectation of the external device