SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
OptiFlash was built with the ability for commands passing through to have 0 latency.
Commands that use the TAG memory have a 3-cycle delay to accommodate ram latencies and any ECC error correction from the RAM.
Commands are stalled when a write to RAM is done either through cache miss return or FLC copy is active.