SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is used to program the Command for host controller
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0FA0 000Eh |
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | CMD_INDEX | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| CMD_TYPE | DATA_PRESENT | CMD_INDEX_CHK_ENA | CMD_CRC_CHK_ENA | SUB_CMD | RESP_TYPE_SEL | ||
| R/W | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:14 | RESERVED | NONE | 0h | Reserved |
| 13:8 | CMD_INDEX | R/W | 0h | This bit shall be set to the command number [CMD0-63, ACMD0-63]. Reset Source: vbus_amod_g_rst_n |
| 7:6 | CMD_TYPE | R/W | 0h |
There are three types of special commands. Suspend, Resume andAbort. These bits shall bet set to 00b for all other commands.
Suspend Command:
If the Suspend command succeeds, the HC shall assume the SD Bus has been released and that it is possible to issue the next command which uses the DAT line. The HC shall de-assert Read Wait for read transactions and stop checking busy for write transactions. The Interrupt cycle shall start, in 4-bit mode. If the Suspend command fails, the HC shall maintain its current state. and the HD shall restart the transfer by setting Continue Request in the Block Gap Control Register.
Resume Command:
The HD re-starts the data transfer by restoring the registers in the range of 000-00Dh. The HC shall check for busy before starting write transfers.
Abort Command:
If this command is set when exe- cuting a read transfer, the HC shall stop reads to the buffer. If this command is set when executing a writetransfer, the HC shall stop driving the DAT line. After issuing the Abort command, the HD should issue a software reset.
3 2 1 0 |
| 5 | DATA_PRESENT | R/W | 0h |
This bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. If is set to 0 for the following:
1. Commands using only CMD line [ex. CMD52].
2. Commands with no data transferbut using busy signal on DAT[0]line [R1b or R5b ex. CMD38].
3. Resume Command.
1 Data present 0 Data not Present |
| 4 | CMD_INDEX_CHK_ENA | R/W | 0h |
If this bit is set to 1, the HC shall check the index field in the response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. If this bit is set to 0, the Index field is not checked.
1 Enable Command Index Check 0 Disable Command Index Check |
| 3 | CMD_CRC_CHK_ENA | R/W | 0h |
If this bit is set to 1, the HC shall check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked.
1 Enable Command CRC Check 0 Disable Command CRC Check |
| 2 | SUB_CMD | R/W | 0h | This bit is added from Version 4.10 to distinguish a main command or sub command [Refer to Section 1.17]. When issuing a main com-mand, this bit is set to 0 and when issuing a sub command, this bit is set to 1. Setting of this bit is checked by Sub Command Status in the Present State register.Host Driver manages whether main or sub command. Host Controller does not refer to this bit to issue a command.
1 Sub Command 0 Main Command |
| 1:0 | RESP_TYPE_SEL | R/W | 0h |
Response Type Select.
3 2 1 0 |