SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
IrDA modes only. The registers TXFLL and TXFLH hold the 13-bit transmit frame length (expressed in bytes). TXFLL holds the least significant bits and TXFLH holds the most significant bits. The frame length value is used if the frame length method of frame closing is used.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 002Ch |
| UART1 | 0281 002Ch |
| UART2 | 0282 002Ch |
| UART3 | 0283 002Ch |
| UART4 | 0284 002Ch |
| UART5 | 0285 002Ch |
| UART6 | 0286 002Ch |
| WKUP_UART0 | 2B30 002Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TXFLH | ||||||
| R | W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7:5 | RESERVED | R | 0h | |
| 4:0 | TXFLH | W | 0h | MSB register used to specify the frame length Reset Source: mod_g_arstn |