SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Mode definition register 3.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0080h |
| UART1 | 0281 0080h |
| UART2 | 0282 0080h |
| UART3 | 0283 0080h |
| UART4 | 0284 0080h |
| UART5 | 0285 0080h |
| UART6 | 0286 0080h |
| WKUP_UART0 | 2B30 0080h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED2 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED2 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED2 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED1 | DIR_EN | DIR_POL | SET_DMA_TX_THRESHOLD | NONDEFAULT_FREQ | DISABLE_CIR_RX_DEMOD | ||
| R | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED2 | R | 0h | |
| 7:5 | RESERVED1 | R | 0h | Reserved |
| 4 | DIR_EN | R/W | 0h | RS-485 External Transceiver Direction Enable Reset Source: mod_g_arstn |
| 3 | DIR_POL | R/W | 0h | RS-485 External Transceiver Direction Polarity. 0 => TX: RTS=0, RX: RTS=1. 1 => TX: RTS=1, RX: RTS=0 Reset Source: mod_g_arstn |
| 2 | SET_DMA_TX_THRESHOLD | R/W | 0h | Enable to set different TX DMA threshold then 64-trigger [usage of new register TX_DNA_THRESHOLD] Reset Source: mod_g_arstn |
| 1 | NONDEFAULT_FREQ | R/W | 0h | Enables[1]/Disables[0] using NONDEFAULT fclk frequencies Reset Source: mod_g_arstn |
| 0 | DISABLE_CIR_RX_DEMOD | R/W | 0h | Disables[1]/Enables[0] CIR RX demodulation 0 Enables CIR RX demodulation 1 Disables CIR RX demodulation |