SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The ASRC can generate interrupt signals whenever interrupt condition is satisfied. These signals are exported on ASRC module boundary and can be used to trigger DMA transactions. There is a dedicated interrupt signal for audio samples write and for audio samples read, respectively.
All channels share common interrupt signals at the ASRC module boundary: infifo_intr and outfifo_intr, for write and read respectively. All groups also share common interrupt signals at the ASRC module boundary: ingrp_intr and outgrp_intr, for write and read respectively.
| Interrupt Event Name | Status Register | Set Register | Clear Register | Description |
|---|---|---|---|---|
| INFIFO_INTR | ASRC_IFIRQENSTS | ASRC_IFIRQENSET | ASRC_IFIRQENCLR | Interrupt indicating that one of the input FIFOs has enough space below the configured threshold. |
| OUTFIFO_INTR | SRC_OFIRQENSTS | ASRC_OFIRQENSET | ASRC_OFIRQENCLR | Interrupt indicating that one of output FIFOs has enough data above the configured threshold. |
| INGROUP_INTR | ASRC_IGIRQENSTS | ASRC_IGIRQENSET | ASRC_IGIRQENCLR | Interrupt indicating that the one of the configured Group interrupts has all of the configured Input FIFOs below their respective threshold. |
| OUTGROUP_INTR | ASRC_OGIRQENSTS | ASRC_OGIRQENSET | ASRC_OGIRQENCLR | Interrupt indicating that one of the configured Group interrupts has all of the configured Output FIFOs above their respective threshold. |
| ERROR_INTR | ASRC_ERIRQENSTS | ASRC_ERIRQENSET | ASRC_ERIRQENCLR | Interrupt indicating one of the streams has received an error condition, FIFO overflow or underflow |