SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
When the DMA handler has completed its ‘N-1’ CBASS0 accesses, read_count is assigned with ‘N-1’.
| Step | Register/Bit Field/Programming Model | Value |
|---|---|---|
| Start the channel | MCSPI_CH(i)CTRL[0] EN | 1 |
| Wait until read_count = N - 1 | ||
| Disable DMA read request | MCSPI_CH(i)CONF[15] DMAR | 0 |
| Wait until last_transfer = TRUE | ||
| Stop the channel | MCSPI_CH(i)CTRL[0] EN | 0 |
| Read the receiver register | MCSPI_RXi | 0x- |
| Increment read_count +1 | ||
| Step | Register/Bit Field/Programming Model | Value |
|---|---|---|
| Read MCSPI_IRQSTATUS | MCSPI_IRQSTATUS | 0x- |
| Write MCSPI_IRQSTATUS to reset channel status bits | MCSPI_IRQSTATUS[channel i bits] | 0b1111 |
| IF: RXi_FULL AND read_count = N | ||
| last_transfer = TRUE | ||
| ENDIF | ||