SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The C7XSS0 and C7XSS1 are a single-core C7xV-256 subsystem with embedded debug capability and features, including:
A summary of the C7XSS0 and C7XSS1 debug capabilities and features is detailed in the following table.
| Capability | Feature | Notes |
|---|---|---|
| Basic Debug | Independent Debug Configuration |
Debug resource configuration is performed over a configuration interface that is isolated from functional traffic |
| ROM Table |
Facilitates discovery of debug resources within debug configuration address space |
|
| Processor Halt | Support user-requested entry into the suspended state | |
| Single Step |
Execution of a single instruction before entering the suspended state |
|
| Software Breakpoints | Software breakpoints are supported via opcode replacement | |
| Hardware Breakpoints | Four Debug Breakpoint resources support hardware breakpoints | |
| Core Regsiter Access | Access to processor core registers | |
| System Memory Access | Access to memory from perspective of CPU | |
| Arm TrustZone Debug Authentication |
Provisioning for DBGEN, NIDEN, SPIDEN, SPNIDEN, SUIDEN, and SUNIDEN |
|
| Cross Triggering | Debug State |
Support for controlling execution state (run, halt) via triggers and creating triggers upon entry into debug state |
| AET | Two channels of AET external triggers (input and output) | |
| AET | Profile Counters |
Two counters can be used to count different events available for gathering statistics on the operation of the processor and memory system. Includes watermark support |
| Application Context Sensitive Trigger |
Supports generation of events based on the context of application execution (e.g. Thread-ID, Virtual Machine ID, Program bus activity, Memory bus activity) |
|
| Visibility and Detection of Events | Provided by CPU, Subsystem, and SOC | |
| Range Detection | Of Program and Memory bus activity | |
| Programmable State Machine | Supports complex, state-based event detection | |
| Trace Stream Filtering/Windowing | Supports the management of trace windows | |
| Trace | Historical Record |
Creates a customized (based on trace stream filtering/windowing) historical account of the CPU’s behavior through the use of different types of trace streams |
| Program Flow Trace |
Records program flow execution, including discontinuities resulting from branches, interrupts, or exceptions |
|
| Cycle Accurate Trace | Records cycle-accurate timing information | |
| Memory Reference Trace | Records data log activity (address, data, address and data) | |
| Event Trace |
Records information about the occurrence, duration, or relationship of one or more events |
|
| Stream Buffer Parameter Trace |
Records the parameters used to start a stream buffer operation allowing off-line reconstruction |
|
| Application Context Trace | Records changes in the context of the application (virtual machine ID, thread-ID) | |
| Stall Control | Support for stalling the C7X processor to avoid Trace overflows | |
| Global Timestamping | Support for attaching a global timestamp to trace traffic | |
| Traffic Monitoring |
Traffic monitoring bus probes are deployed within C7XSS0 memory subsystem |