SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Configures cluster level characteristics
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| Instance Name | Physical Address |
|---|---|
| MAIN_SEC_MMR0 | 45A0 E040h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CLSTR14_CONFIG0_ENDIAN | CLSTR14_CONFIG0_CPU_SYS_RISCV_MODE | RESERVED | |||||
| R/W | R/W | NONE | |||||
| 0h | 0h | 0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | CLSTR14_CONFIG0_EL2SIZE | ||||||
| NONE | R | ||||||
| 0h | 0h | 0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CLSTR14_CONFIG0_L2SIZE | CLSTR14_CONFIG0_L1DSIZE | CLSTR14_CONFIG0_L1PSIZE | |||||
| R | R | R | |||||
| 8h | 2h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLSTR14_CONFIG0_L1PSIZE | CLSTR14_CONFIG0_VWIDTH | CLSTR14_CONFIG0_RISCV | CLSTR14_CONFIG0_MMA | CLSTR14_CONFIG0_CPU | |||
| R | R | R | R | R | |||
| 0h | 2h | 1h | 1h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | CLSTR14_CONFIG0_ENDIAN | R/W | 0h | Reset value of Endian control. 0 - Little Endian 1 - Big Endian Reset Source: mod_g_rst_n |
| 30 | CLSTR14_CONFIG0_CPU_SYS_RISCV_MODE | R/W | 0h | Activates CPU Booting in RiscV Mode 0 - Boot in C7x ISA Mode 1 - Boot in RiscV ISA Mode Reset Source: mod_g_rst_n |
| 29:20 | RESERVED | NONE | 0h | Reserved |
| 18:16 | CLSTR14_CONFIG0_EL2SIZE | R | 0h | EL2 Size Field values (others are reserved): 3'b000 - None 3'b001 - 1 MB 3'b010 - 1.5 MB 3'b011 - 2 MB 3'b100 - 2.5 MB 3'b101 - 3 MB 3'b110 - 3.5MB 3'b111 - 4 Mb Reset Source: mod_g_rst_n |
| 15:11 | CLSTR14_CONFIG0_L2SIZE | R | 8h | L2 Size Field values (others are reserved): 5'b00000 - None 5'b00001 - 512 KB 5'b00010 - 768 KB 5'b00011 - 1 MB 5'b00100 - 1.25 MB 5'b00101 - 1.5 MB 5'b00110 - 1.75 MB 5'b00111 - 2 MB 5'b01000 - 2.25 MB 5'b01001 - 2.5 MB 5'b01010 - 2.75 MB 5'b01011 - 3 MB 5'b00100 - 3.25 MB 5'b01101 - 3.5 MB 5'b01110 - 3.75 MB 5'b01111 - 4 MB 5'b10000 - 4.5 MB 5'b10001 - 5 MB 5'b10010 - 5.5 MB 5'b10011 - 6 MB 5'b10100 - 6.5 MB 5'b10101 - 7 MB 5'b10110 - 7.5 MB 5'b10111 - 8 MB Reset Source: mod_g_rst_n |
| 10:9 | CLSTR14_CONFIG0_L1DSIZE | R | 2h | L1D Cache Size Field values (others are reserved): 2'b00 - 32 KB 2'b01 - 48 KB 2'b10 - 64 KB 2'b11 - 128 KB Reset Source: mod_g_rst_n |
| 8:7 | CLSTR14_CONFIG0_L1PSIZE | R | 0h | L1P Cache Size Field values (others are reserved): 2'b00 - 32 KB 2'b01 - 48 KB 2'b10 - 64 KB 2'b11 - 128 KB Reset Source: mod_g_rst_n |
| 6:5 | CLSTR14_CONFIG0_VWIDTH | R | 2h | Vector Width Field values (others are reserved): 2'b00 - 64 bit 2'b01 - 128 bit 2'b10 - 256 bit 2'b11 - 512 bit Reset Source: mod_g_rst_n |
| 4 | CLSTR14_CONFIG0_RISCV | R | 1h | RISCV ISA Support Field values (others are reserved): 1'b0 - Not Supported 1'b1 - Supported Reset Source: mod_g_rst_n |
| 3:2 | CLSTR14_CONFIG0_MMA | R | 1h | MMA Type Field values (others are reserved): 2'b00 - Reserved 2'b01 - Reserved 2'b10 - MMA2 2'b11 - MMA2p1 Reset Source: mod_g_rst_n |
| 1:0 | CLSTR14_CONFIG0_CPU | R | 0h | CPU Type Field values (others are reserved): 2'b00 - Reserved 2'b01 - Reserved 2'b10 - Reserved 2'b11 - AC72 R10 Reset Source: mod_g_rst_n |