SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The FLC Config Register contains the configuration values for the FLC.
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| Instance Name | Physical Address |
|---|---|
| RL2_0 | 2500 0104h |
| RL2_0 | 2500 1104h |
| RL2_2 | 2500 2104h |
| RL2_3 | 2500 3104h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| FIFO_BYPASS | RESERVED | FLC_EXCNT | |||||
| R/W | NONE | R/W | |||||
| 0h | 0h | 0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ASMNUM | |||||||
| R | |||||||
| 5h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RANGES | |||||||
| R | |||||||
| 4h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | FIFO_BYPASS | R/W | 0h | Setting this bit will cause the write to remote memory for a cache miss or FLC return to forces stalls on the read returns if any other data phase for a cache miss or FLC return is received. This can cause stalls on the write to force stalls on the read. |
| 30:27 | RESERVED | NONE | 0h | Reserved |
| 26:24 | FLC_EXCNT | R/W | 0h | The number of extra requests the FLC can send. The maximum value is 4 anything greater will default to 4. This value + 1 is the number of Reassembly Buffers used for FLC so if cache misses needed to be supported this value should be set to 4 or lower. The number of cache misses that will be allowed to be outstanding while FLC is running will be 5 - (FLC_EXCNT + 1). |
| 23:16 | RESERVED | NONE | 0h | Reserved |
| 15:8 | ASMNUM | R | 5h | Number of Reassembly Buffer supported |
| 7:0 | RANGES | R | 4h | Number of FLC ranges supported |