SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The reference clock MCU_PLL0_REF_CLK for the PLL in MCU domain is chosen between the internal high-frequency (HF) oscillator with external crystal (HFOSC0) and 12.5-MHz free-running RC oscillator. The selection is made through MCU_CTRL_MMR_CFG0_MCU_PLL_CLKSEL[8] MCU_PLL_CLKSEL_CLKLOSS_SWTCH_EN, see PLL Top Level Domain Reference Clock Selection.
| MCU_CTRL_MMR_CFG0_MCU_PLL_CLKSEL(1)[8] MCU_PLL_CLKSEL_CLKLOSS_SWTCH_EN |
MCU_PLL0_REF_CLK |
|---|---|
| 0 (default) | HFOSC0_CLK |
| 1 | CLK_12M_RC if clock loss is detected or HFOSC0_CLK if clock loss is not detected |