SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Interrupt Enable Clear Register 0
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 0070 91C0h |
| 32 | 31 | 30 | 29 | 28 | 27 | 26 | 25 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 |
| RESERVED | TXMEM_ENABLE_CLR | ||||||
| NONE | R/W1TC | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | RESERVED | NONE | 0h | Reserved |
| 0 | TXMEM_ENABLE_CLR | R/W1TC | 0h | Interrupt Enable Clear Register for txmem_pend |