SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Indirect Memory Control and Status Register This register is used to control the behavior of the indirect memory controller.
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 0030h |
| C7X256V1_DEBUG | 0007 3800 0030h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | MEM_RESET_PORT | RESERVED | MEM_ACC_CODE | ||||
| NONE | R/W | NONE | R | ||||
| 0h | 1h | 0h | 0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| MEM_ERR_CODE | MEM_BUS_STAT | MEM_ERR_OVERRUN | MEM_PORT_STAT | ||||
| R | R | R | R | ||||
| 0h | 1h | 0h | 0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| MEM_QUAL_PSTMTRM | MEM_QUAL_VMID | MEM_QUAL_PROC | MEM_QUAL_DCTXT | RESERVED | MEM_ACC_SIZE | ||
| R/W | R/W | R/W | R/W | NONE | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MEM_PAGE | MEM_IGNORE_CTXT | MEM_IGNORE_DBGM | MEM_ADDR_INC | MEM_RW | ||
| NONE | R/W | R/W | R/W | R/W | R/W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | RESERVED | NONE | 0h | Reserved |
| 29 | MEM_RESET_PORT | R/W | 1h | Port Reset |
| 28 | RESERVED | NONE | 0h | Reserved |
| 27:24 | MEM_ACC_CODE | R | 0h | Indicates the access code returned for the last read transaction |
| 23:20 | MEM_ERR_CODE | R | 0h | Indicates the bus error code returned for a transaction This field indicates the memory access error code returned by the subsystem interconnect The first non-zero error is captured and held until it is cleared by a port reset |
| 19 | MEM_BUS_STAT | R | 1h | Indicates the bus status [ready state] of the processor interface selected by MEM_PAGE This bit indicates the current availability state [the bus ready value] for the interface selected by MEM_PAGE It is used by the debug agent to determine if the interface is in a hung state |
| 18 | MEM_ERR_OVERRUN | R | 0h | Indicates the state of the access port This field indicates that the settings of the indirect access port [control, context, data, or address] registers have changed before a previous access completed Once it is set to 1 it stays asserted until it is cleared by a port reset |
| 17:16 | MEM_PORT_STAT | R | 0h | Pending Memory Request Completed This bit indicates the status of the memory port |
| 15 | MEM_QUAL_PSTMTRM | R/W | 0h | Post Mortem Qualification This bit controls if a memory access is submitted as part of a postmortem analysis acitivty This bit will be set only when normal debug initiated accesses are no longer possible due to a system crash When set, the CPU will service an indirect access port request independent of all other memory qualifiers or normally required architectural state dependencies |
| 14 | MEM_QUAL_VMID | R/W | 0h | VMID Qualification This bit controls if a VMID context match is required of accesses submitted by the indirect controller The VMID reference is programmed using DBG_INDRCT_CTXT2 |
| 13 | MEM_QUAL_PROC | R/W | 0h | Processor State Qualification Enable This bit controls if a processor state match is required of accesses submitted by the indirect controller The processor states of interest are programmed using DBG_INDRCT_CTXT2 |
| 12 | MEM_QUAL_DCTXT | R/W | 0h | Debug Context Qualification Enable This bit controls if a DCTXT context match is required of accesses submitted by the indirect controller The DCTXT reference and mask are programmed using DBG_INDRCT_CTXT0 and DBG_INDRCT_CTXT1 |
| 11 | RESERVED | NONE | 0h | Reserved |
| 10:8 | MEM_ACC_SIZE | R/W | 0h | Access size of the next transaction |
| 7 | RESERVED | NONE | 0h | Reserved |
| 6:4 | MEM_PAGE | R/W | 0h | Page designator for the next access This bit defines the page index of the memory page targeted for subsequent transactions The parameters of the pages supported in the system are available in the DBG_INDRCT_CAP register |
| 3 | MEM_IGNORE_CTXT | R/W | 0h | Ignore Context This bit determines whether memory/register accesses through the indirect controller will honor or ignore IDS and debug context changes |
| 2 | MEM_IGNORE_DBGM | R/W | 0h | Ignore DBGM When Halting This bit is used to grant privileges to ignore the DBGM flag when servicing a request to access memory or registers via the Indirect Access Port |
| 1 | MEM_ADDR_INC | R/W | 0h | Auto increment address on each access This bit determines if the address used for the memory access auto-increments For read transactions, the auto-increment occurs when the previous value is read from the data registers This will automatically launch another read transaction from the new address For write transactions, the auto-increment occurs when the write completes A new write is not launched until new data is written into the data registers The auto-increment feature is disabled on any error [the bit stays set] and is not re-enabled until the error is cleared |
| 0 | MEM_RW | R/W | 0h | R/W Control for next accesses This bit determines if the port is executing read or write operations |