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SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1

14.7.2.3.2.27 MCSPI_CH3CONF Register

3.2.27.1 MCSPI_CH3CONF Register (Offset = 168h) [reset = 60000h]

This register is dedicated to the configuration of the channel 3

Table 14-11746 Instance Table

Instance Name	Physical Address
MCSPI0	2010 0168h
MCSPI1	2011 0168h
MCSPI2	2012 0168h
MCSPI3	2013 0168h
MCSPI4	2014 0168h

Figure 14-5817 MCSPI_CH3CONF Name Register

31	30	29	28	27	26	25	24
RESERVED_0		CLKG	FFER	FFEW	TCS3		SBPOL
R		R/W	R/W	R/W	R/W		R/W
0h		0h	0h	0h	0h		0h
23	22	21	20	19	18	17	16
SBE	RESERVED_1		FORCE	TURBO	IS	DPE1	DPE0
R/W	R		R/W	R/W	R/W	R/W	R/W
0h	0h		0h	0h	1h	1h	0h
15	14	13	12	11	10	9	8
DMAR	DMAW	TRM		WL
R/W	R/W	R/W		R/W
0h	0h	0h		0h
7	6	5	4	3	2	1	0
WL	EPOL	CLKD				POL	PHA
R/W	R/W	R/W				R/W	R/W
0h	0h	0h				0h	0h

Table 14-11747 MCSPI_CH3CONF Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	RESERVED_0	R	0h	read returns 0
29	CLKG	R/W	0h	Clock divider granularity This register defines the granularity of channel clock divider: power of two or one clock cycle granularity When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio Then The clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values 0 Clock granularity of power of 2 1 One clock cycle granularity
28	FFER	R/W	0h	FIFO enabled for receive:Only one channel can have this bit field set 0 The buffer is not used to receive data. 1 The buffer is used to receive data.
27	FFEW	R/W	0h	FIFO enabled for Transmit:Only one channel can have this bit field set 0 The buffer is not used to transmit data. 1 The buffer is used to transmit data.
26:25	TCS3	R/W	0h	Chip Select Time Control This 2-bits field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock 0 0.5 clock cycle 1 1.5 clock cycles 2 2.5 clock cycles 3 3.5 clock cycles
24	SBPOL	R/W	0h	Start bit polarity 0 SPICLK is held low during the INACTIVE state 1 SPICLK is held high during the INACTIVE state
23	SBE	R/W	0h	Start bit enable for SPI transfer 0 Default MCSPI transfer length as specified by WL bit field 1 Start bit D/CX added before MCSPI transfer polarity is defined by MCSPI_CHCONF_0[24] SBPOL
22:21	RESERVED_1	R	0h	read returns 0
20	FORCE	R/W	0h	Manual SPIEN assertion to keep SPIEN active between SPI words [single channel controller mode only] 0 Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF_0/1/2/3[6] EPOL=0, and drives it high when MCSPI_CHCONF_0/1/2/3[6] EPOL=1. 1 Writing 1 into this bit drives high the SPIEN line when MCSPI_CHCONF_0/1/2/3[6] EPOL=0, and drives it low when MCSPI_CHCONF_0/1/2/3[6] EPOL=1.
19	TURBO	R/W	0h	Turbo mode 0 Turbo is deactivated (recommended for single MCSPI word transfer). 1 Turbo is activated to maximize the throughput for multiple MCSPI words transfer.
18	IS	R/W	1h	Input Select 0 Data line 0 (SPIDAT[0]) selected for reception 1 Data line 1 (SPIDAT[1]) selected for reception
17	DPE1	R/W	1h	Transmission Enable for data line 1 [SPIDATAGZEN[1]] 0 Data line 1 (SPIDAT[1]) selected for transmission 1 No transmission on Data Line1 (SPIDAT[1])
16	DPE0	R/W	0h	Transmission Enable for data line 0 [SPIDATAGZEN[0]] 0 Data Line0 (SPIDAT[0]) selected for transmission 1 No transmission on data line 0 (SPIDAT[0])
15	DMAR	R/W	0h	DMA Read request The DMA Read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel The DMA Read request line is deasserted on read completion of the receive register of the channel 0 DMA read request disabled 1 DMA read request enabled
14	DMAW	R/W	0h	DMA Write request The DMA Write request line is asserted when The channel is enabled and the transmitter register of the channel is empty The DMA Write request line is deasserted on load completion of the transmitter register of the channel 0 DMA write request disabled 1 DMA write request enabled
13:12	TRM	R/W	0h	Transmit/Receive modes 0 Transmit-and-receive mode 1 Receive-only mode 2 Transmit-only mode 3 Reserved
11:7	WL	R/W	0h	SPI word length 0 Reserved 1 Reserved 2 Reserved 3 The MCSPI word is 4 bits long 4 The MCSPI word is 5 bits long 5 The MCSPI word is 6 bits long 6 The MCSPI word is 7 bits long 7 The MCSPI word is 8 bits long 8 The MCSPI word is 9 bits long 9 The MCSPI word is 10 bits long A The MCSPI word is 11 bits long B The MCSPI word is 12 bits long C The MCSPI word is 13 bits long D The MCSPI word is 14 bits long E The MCSPI word is 15 bits long F The MCSPI word is 16 bits long 10 The MCSPI word is 17 bits long 11 The MCSPI word is 18 bits long 12 The MCSPI word is 19 bits long 13 The MCSPI word is 20 bits long 14 The MCSPI word is 21 bits long 15 The MCSPI word is 22 bits long 16 The MCSPI word is 23 bits long 17 The MCSPI word is 24 bits long 18 The MCSPI word is 25 bits long 19 The MCSPI word is 26 bits long 1A The MCSPI word is 27 bits long 1B The MCSPI word is 28 bits long 1C The MCSPI word is 29 bits long 1D The MCSPI word is 30 bits long 1E The MCSPI word is 31 bits long 1F The MCSPI word is 32 bits long
6	EPOL	R/W	0h	SPIEN polarity 0 SPICLK is held low during the INACTIVE state 1 SPICLK is held high during the INACTIVE state
5:2	CLKD	R/W	0h	Frequency divider for SPICLK [only when the module is a Controller SPI device] A programmable clock divider divides the SPI reference clock [CLKSPIREF] with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data By default the clock divider ratio has a power of two granularity when MCSPI_CHCONF[CLKG] is cleared, Otherwise this register is the 4 LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] registerThe value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0 0 1 1 2 2 4 3 8 4 16 5 32 6 64 7 128 8 256 9 512 A 1024 B 2048 C 4096 D 8192 E 16384 F 32768
1	POL	R/W	0h	SPICLK polarity 0 SPICLK is held low during the INACTIVE state 1 SPICLK is held high during the INACTIVE state
0	PHA	R/W	0h	SPICLK phase 0 Data are latched on odd-numbered edges of SPICLK. 1 Data are latched on even-numbered edges of SPICLK.