SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register controls the various parameters of the OCP interface
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| TIMER0 | 0240 0010h |
| TIMER1 | 0241 0010h |
| TIMER2 | 0242 0010h |
| TIMER3 | 0243 0010h |
| TIMER4 | 0244 0010h |
| TIMER5 | 0245 0010h |
| TIMER6 | 0246 0010h |
| TIMER7 | 0247 0010h |
| TIMER8 | 0248 0010h |
| TIMER9 | 0249 0010h |
| TIMER10 | 024A 0010h |
| TIMER11 | 024B 0010h |
| TIMER12 | 024C 0010h |
| TIMER13 | 024D 0010h |
| TIMER14 | 024E 0010h |
| TIMER15 | 024F 0010h |
| WKUP_TIMER0 | 2B10 0010h |
| WKUP_TIMER1 | 2B11 0010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | IDLEMODE | EMUFREE | SOFTRESET | ||||
| NONE | R/W | R/W | R/W | ||||
| 0h | 2h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED | NONE | 0h | Reserved |
| 3:2 | IDLEMODE | R/W | 2h | Idle Mode 0 local target's idle state follows
(acknowledges) the system's idle reuquests
unconditionaly, i.e. regardless of the IP
module's internal requirments. Back mode,
for debug only.
1 local target never enteres idle state. Back
mode, for debug only.
2 local target's idle state eventually
follows (acknowledges) the systems' idle
requests, depending on the IP module's
internal requirments. IP module shall not
generate (IRQ- or DMA-request-releated)
wakuep events.
3 local target's idle state eventually
follows (acknowledges) the system's idle
requests, depending on the IP module's
internal requirents. IP module may generate
(IRQ- or DMA-request-related) wakeup events
when in idle state. Mode is only relevant
if the appropriate IP module "swakeup"
output(s) is (are) impolemented. |
| 1 | EMUFREE | R/W | 0h | Emulation Mode 0 The timer is frozen in emulation mode
(PI_SUSPEND signal active)
1 The timer runs free, regardless of
PI_SUSPEND value |
| 0 | SOFTRESET | R/W | 0h | Software reset 0 Read: Reset Done, no pending action Write:
no action
1 Read: Reset ongoing Write: initiate
software reset |