SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Figure 12-223 shows the sequence to finalize a SD Command when response check is disabled. There is a possibility that some errors (Command Index/End bit/CRC/Timeout Error) occur during this sequence. If response check is enabled, error is indicated by Response Error Interrupt.
Figure 12-223 Command Complete Sequence