SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Contains the lower 16 bits of the boot vector location for R5 Core1
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| Instance Name | Physical Address |
|---|---|
| MAIN_SEC_MMR0 | 45A0 1194h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CLSTR1_CORE1_BOOTVECT_HI_VECT_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLSTR1_CORE1_BOOTVECT_HI_VECT_ADDR | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15:0 | CLSTR1_CORE1_BOOTVECT_HI_VECT_ADDR | R/W | 0h | Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]. Reset Source: sys_por_rst_n |