The MLBSS supports the following features:
- 3-pin MediaLB 3.3V LVCMOS I/Os compliant to MediaLB Physical Layer and Link Layer Specification v4.2
- 6-pin MediaLB+ low-voltage differential signaling (LVDS) I/Os (3 differential pairs) compliant to MediaLB Physical Layer and Link Layer Specification v4.2
- MediaLB core functionality compliant to MediaLB Physical Layer and Link Layer Specification v4.2
- Supports 256/512/1024Fs in 3-pin mode
- Supports 2048Fs in 6-pin mode using a 1:1 recovered-to-external clock ratio
- Supports 3072/4096Fs in 6-pin mode using a 2:1 recovered-to-external clock ratio
- Supports all types of transfers (synchronous stream data, asynchronous packet data, control message data, and isochronous data) over 64 logical channels
- Supports single 32-bit slave interface for configuration
- Supports single 32-bit master interface with burst capability for DMA transfers into system memory. The maximum burst size is 32 Bytes
- RAT module on the master interface to translate the 32-bit address into a 40-bit system address
- ECC aggregator to protect internal memories
- Has 16 KB buffer for all types of transfers in the subsystem
- Dedicated register for controlling the MLBSS priority on the system interconnect