SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Mode Bit Configuration Register
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC4 0028h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RX_CRC_DATA_LOW_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RX_CRC_DATA_UP_FLD | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CRC_OUT_ENABLE_FLD | MODE_BIT_RESV1_FLD | CHUNK_SIZE_FLD | |||||
| R/W | R | R/W | |||||
| 0h | 0h | 2h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MODE_FLD | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | RX_CRC_DATA_LOW_FLD | R | 0h | RX CRC data [lower] The first CRC byte returned after RX data chunk. |
| 23:16 | RX_CRC_DATA_UP_FLD | R | 0h | RX CRC data [upper] The second CRC byte returned after RX data chunk. |
| 15 | CRC_OUT_ENABLE_FLD | R/W | 0h | CRC# output enable bit When enabled, the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly. |
| 14:11 | MODE_BIT_RESV1_FLD | R | 0h | Reserved |
| 10:8 | CHUNK_SIZE_FLD | R/W | 2h | It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers. |
| 7:0 | MODE_FLD | R/W | 0h | These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled. |