SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Register GTXFIFOSIZ 6
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C318h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TXFSTADDR_N | |||||||
| R/W | |||||||
| FCCh | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TXFSTADDR_N | |||||||
| R/W | |||||||
| FCCh | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TXFDEP_N | |||||||
| R/W | |||||||
| 209h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TXFDEP_N | |||||||
| R/W | |||||||
| 209h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | TXFSTADDR_N | R/W | FCCh | Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words. Reset Source: rst_mod_g_rst_n |
| 15:0 | TXFDEP_N | R/W | 209h | TxFIFO Depth This field contains the depth of TxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 32,768 For more information, see "Integrating the Controller" chapter in the User Guide. Reset Source: rst_mod_g_rst_n |