SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the hardware configuration options
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C154h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| GHWPARAMS5_31_28 | GHWPARAMS5_27_22 | ||||||
| R | R | ||||||
| 0h | 10h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| GHWPARAMS5_27_22 | GHWPARAMS5_21_16 | ||||||
| R | R | ||||||
| 10h | 20h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| GHWPARAMS5_15_10 | GHWPARAMS5_9_4 | ||||||
| R | R | ||||||
| 8h | 8h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GHWPARAMS5_9_4 | GHWPARAMS5_3_0 | ||||||
| R | R | ||||||
| 8h | 8h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | GHWPARAMS5_31_28 | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 27:22 | GHWPARAMS5_27_22 | R | 10h | DWC_USB3_DFQ_FIFO_DEPTH Reset Source: rst_mod_g_rst_n |
| 21:16 | GHWPARAMS5_21_16 | R | 20h | DWC_USB3_DWQ_FIFO_DEPTH Reset Source: rst_mod_g_rst_n |
| 15:10 | GHWPARAMS5_15_10 | R | 8h | DWC_USB3_TXQ_FIFO_DEPTH Reset Source: rst_mod_g_rst_n |
| 9:4 | GHWPARAMS5_9_4 | R | 8h | DWC_USB3_RXQ_FIFO_DEPTH Reset Source: rst_mod_g_rst_n |
| 3:0 | GHWPARAMS5_3_0 | R | 8h | DWC_USB3_BMU_BUSGM_DEPTH Reset Source: rst_mod_g_rst_n |